Senior Applications Engineering Manager

CPL

CORK

What you will do and what you need to be considered. Manage a team of Front End Engineers to empower customers with setting up their design. Substantial experience with Verilog is required, as are excellent logic and debug skills. Define and document digital microarchitechure. An understanding of Lint checks, FPGA or emulation platform, synthesis timing constraints. Understanding of proper handling of multiple asynchronous clock domains and their crossings. Firmware development of embedded microcontroller systems is beneficial. Excellent communiaction skills. Prior management experince and building teams is a bonus.

1360 days ago